Find the FPGA and ASIC RTL, latency, CDC, and timing risks before they cost you months.
A fixed-scope 10-business-day audit for trading firms running ultra-low-latency pipelines, AI accelerator teams scaling inference cores, and GNSS/SDR/signal-processing groups building high-throughput RTL on FPGA or ASIC pre-tapeout.
Charter pricing: $9,995 fixed scope while the charter window is open. Mutual NDA before any RTL touches my machine.
What you get for $9,995
- 01Module-by-module critical path analysis across your full RTL hierarchy. Every path with less than 10% timing margin against your target clock period flagged, ranked, and mapped to its root cause.
- 02Microarchitecture bottleneck identification — pipelining gaps, fanout cliffs, clock-domain crossings missed by your CDC tools, FIFO depth miscalibrations, memory port contention.
- 03Prioritized mitigation roadmap. Every issue ranked by fix-cost vs. timing-margin recovery, so you know what to attack first and what to leave alone.
- 04Revised timing closure plan including SDC/MMMC constraint recommendations, floorplan suggestions for the worst paths, and a realistic re-closure timeline.
- 05Direct senior-engineer access throughout — no project manager, no junior handoff, no "we'll get back to you next week."
- 06Written report your team and stakeholders can act on independently — formatted for engineering reviews, not a sales pitch.
You work with me directly, in writing — every answer and every finding is a document your team can act on and forward, not a meeting someone has to sit through. Writing isn't less access; it's a complete record of the work.
Payment structure: $5,000 refundable deposit to reserve your audit slot. $4,995 remainder invoiced at audit kickoff, once your materials are in and the review begins.
Refund: deposit fully refundable if your design falls outside audit scope after I review your intake.
John Bagshaw
John Bagshaw is a Senior FPGA Design Engineer with 8+ years across FPGA RTL, with deep experience in HFT pipelines, AI accelerators (KVCache open-source), GNSS, CXL 2.0, and DDR4 — directly applicable to ASIC RTL audits pre-tapeout. Platforms: AMD Zynq UltraScale+, AMD Versal, and Intel Agilex 7.
Recent open-source: github.com/taitashaw/cxl-kv-forge-qos — an 8-tenant LLM KV-cache QoS controller with setup and hold closed post-route at 400 MHz (WNS +0.033 ns, TNS 0/0) on xczu7ev Zynq UltraScale+, a 13/13 XSim pass, and timing and utilization reports committed to the repo.
One block, reviewed before tapeout.
Pick the block that worries you most. We agree the checks before work starts: arbitration and backpressure, clock and reset crossings, test gaps, and the critical path.
- ■The block's RTL and its interface definitions
- ■Your clock and constraint files
- ■The testbench, if one exists
- ■Synthesis or route timing reports, if you have them
- ■Written findings, ranked by risk
- ■For each: what fails, the evidence, and a fix direction
- ■Delivered 5 business days after the inputs arrive
- ■Findings only, not a sign-off
Two findings from my own open-source design, in the format you receive. Source and reports on GitHub.
Two queued requests produced four grants. The head request issued 4 times and the next one never issued, so its data was lost.
Worst setup path missed by 0.192 ns, 9,123 endpoints failing. 72% of the path was routing, crossing three module boundaries.
Price and terms are in the pricing section below.
$2,500 one-block RTL risk review
One block you choose, plus its interfaces. We agree the checks before work starts: arbitration and backpressure, clock and reset crossings, test gaps, and the critical path when you can share synthesis or implementation timing reports.
Written findings ranked by risk, 5 business days after the agreed inputs arrive.
Findings only, not fixes and not a sign-off. Paid in full once we agree the scope, so you never pay for a block that turns out to be out of scope. If you book the audit within 60 days, the $2,500 counts toward its $5,000 deposit: you pay $2,500 more to reserve, then the $4,995 balance.
$9,995 fixed-scope audit
$5,000 refundable deposit reserves your slot, credited in full toward the $9,995 audit; the $4,995 balance is invoiced at kickoff.
Once we confirm the scope together, the $5,000 deposit reserves your slot. Kickoff docs land within 2 business hours of payment; the full written findings come at the end of the 10-business-day audit.
Risk reversal: deposit fully refundable if your design falls outside audit scope after I review your intake.
One slipped FPGA tape-out costs $50K–$200K in engineering-month burn, plus 3–6 months of schedule slip and potential loss of the design win. A respin on a complex SoC FPGA averages $80K–$150K all-in. A pre-tape-out audit at $9,995 buys you a senior FPGA engineer's complete review of your critical paths and microarchitecture risks. The ROI calculation is not $9,995 vs. an hourly contractor rate — it is $9,995 to avoid $50K–$200K in downside. At the floor, that is a 5× return. At the ceiling, 20×.
Charter pricing holds $9,995 fixed scope while the charter window is open. Fixed prices, fixed scope: no hourly meter, no scope creep.
After you pay the $5,000 deposit, I send the kickoff intake doc and the mutual NDA within 2 business hours. If the intake doc reveals the audit is not a fit for your system, the deposit is refunded in full within 48 hours. You only commit beyond the deposit once we've both confirmed scope in writing. Deposit fully refundable if your design falls outside audit scope after I review your intake.
What teams ask before they commit.
Tell me what you are running.
Five fields plus context. I review every submission personally and reply by email to confirm the scope before any payment.