Verified semiconductor talent

Hire FPGA and ASIC engineers who already proved it.

Every engineer here passed a scored technical interview in their specialization. You read the category breakdown before you talk to anyone.

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Free to browse. Verification is one 30-minute interview, and engineers keep 100% of their billings.

Companies: post a role, get matched with scored candidatesEngineers: keep 100% of your rate, zero commission

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4scored stages per profile
9specializations
0%commission for engineers
BUILT FOR TEAMS HIRING IN
AI AcceleratorsCXL / MemoryHFTDefenseAutomotiveData Center
Illustrative
A
FPGA / RTL Design
Verified · 8 yrs · Zynq UltraScale+ · Agilex 7
Conceptual depth88
Design diagram84
Work sample81
Defense86
This is the breakdown you see on every profile, before first contact.
RTL Latency Audit

Shipping a latency or determinism claim? De-risk the RTL before the demo.

A fixed-scope review by a senior FPGA engineer. Your timing, CDC, reset, and datapath are examined against the claim your product makes, and you receive a prioritized findings report. No open-ended consulting.

  • Timing closure and critical-path review at your target clock
  • Clock-domain-crossing and reset-domain integrity check
  • Datapath and pipeline latency against your stated number
  • Prioritized findings, ranked by risk to the claim
$9,995 · fixed scope
$5,000 refundable deposit reserves your slot · senior FPGA engineer, prioritized findings report
Reserve your slot — $5,000 depositRead the sample reportSee the audit scope
Open roles

Open roles on the platform.
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Every posting is reviewed before publication and states its vacancy status. Verified engineers are matched first: get verified to be considered.

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Why you can trust the vetting

Proof over promises, starting with who built it.

ShawSilicon is run by a working FPGA engineer, not a recruiter. One scoring scale for everyone, and a verified pool that's live today — engineers you can browse now, not a sign-up list.

JB
John Bagshaw — Founder
Senior FPGA Design Engineer · 8+ years · CXL 2.0, HFT, AI accelerators, DDR4 pipelines

The same engineer who designs the structured technical interview ships timing-closed RTL. His public benchmarks include a GNSS spoof/jam detector at 488.76 MHz, with flashattn-softmax and kvcache-compress both closed at 400 MHz. The bar on ShawSilicon is the bar he holds himself to.

github flashattn-softmax-engine · 400 MHzgithub kvcache-compress-engine · 400 MHzgithub kvcache-attention-frontendgithub @taitashaw

What the interview measures

One structured technical interview in your specialization — about 30 minutes, scored stage by stage on the same scale for everyone.

Conceptual depthDesign diagramWork sampleDefense

Sample questions

Real items from the FPGA / RTL Design track — the kind each engineer answers before any grade is shown. No multiple choice, no LeetCode.

  1. Architecture90s

    You have 1,000 18-bit coefficients for a filter and need to store them on a Xilinx UltraScale FPGA. Walk through your decision process for choosing between BRAM, URAM, distributed RAM, and ROM inference — including resource cost, latency, and read port requirements.

  2. Clock-domain crossing120s

    Your 50 MHz write domain updates a 32-bit configuration register and signals a 200 MHz read domain to latch it. In lab, the read domain occasionally reads a mix of old and new bits — simulation was clean. Diagnose why the 2-FF synchronizer approach fails for multi-bit buses, design a correct toggle-handshake CDC scheme in RTL, and list the FPGA synthesis attributes your design requires.

  3. Timing closure120s

    You run timing analysis on a Xilinx UltraScale design and see this path report: setup slack = -0.3ns, data path delay = 4.8ns (3.1ns logic, 1.7ns route), clock path skew = +0.15ns, clock uncertainty = 0.035ns. Walk through where the slack is being lost and propose three concrete fixes, ranked by effort.

The grade is the product

Each engineer is scored on one scale. You see it; they see it. No black box.

A+Top of the poolscore ≥ 90
AStrong hirescore ≥ 80
B+Solid, specialization-matchedscore ≥ 70
BLowest letter gradescore ≥ 60

Letter grades are independent of the gate. Verified at 51 and up. 51–59 shows as Credible, verified but below a B. Every verified engineer is company-facing; the browse set is ranked by score, not gated a second time.

A real, verified pool

Live verified engineers you can browse today, with new tracks opening.

Verified engineers, strongest in FPGA and RTL
~30mstructured interview, 10 questions, scored by category

For FPGA and semiconductor engineers

Prove it once on a test built by an engineer who holds the same bar. Get matched only to roles that fit your specialization, and keep 100% of your billings.

Start verification

One structured interview — about 30 min — free — keep 100% of your billings.

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